In order to meet the forecasts of the ITRS (International Technology Roadmap for Semiconductors) for future generations of transistors, it is helpful to change the architecture of MOSFET.
The ITRS states that an increase in the mobility of carriers in the channel of transistors is becoming helpful to maintain the gain in performance for generations of transistors for which the gate lengths are less than 100 nm.
To do this, it is, for example, possible to use substrates based on strained silicon. It is also possible to use modules, or internal layers in the devices, which, through their intrinsic stress, place the transistor in tension or in compression.
The documents “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystal Orientations” of M. Yang et al., Electron Devices Meeting 2003 Technical Digest, IEEE International, December 2003, pages 18.7.1 to 18.7.4, and “On the Integration of CMOS with Hybrid Crystal Orientations”, of M. Yang et al., 2004 Symposium on VLSI Technology, Digest of Technical Papers, June 2004, pages 160 to 161, disclose a device formed on a silicon substrate with hybrid crystalline orientations. The device comprises an NMOS transistor formed on a part of a substrate, the crystalline orientation of which is (100) and a PMOS transistor on a part of the substrate, the crystalline orientation of which is (110). The part of the substrate on which one of the two transistors is formed is of an SOI type. The other part of the substrate on which the other of the two transistors is formed is of a bulk type. This type of structure also enables the mobility of carriers in the channel of the transistors to be increased. This type of device may have, in particular, the disadvantage that the two transistors have very different properties and operation. In addition, the advantage of a SOI substrate compared to a bulk type substrate may only be obtained for one of the two transistors. Finally, it may not be possible to have a back control, or “ground plane”, for the transistor located on the SOI part, since this would affect the behavior of the transistor located on the bulk part of the substrate.
The document “Back-Gated CMOS on SOIAS for dynamic threshold voltage control” of I.Y. Yang et al., IEEE Trans. on Elec. Devices, vol. 44, no. 5, May 1997, pages 822 to 831, discloses a double gate type CMOS on SOI device with connection of the back gates, or controls. The thickness of the buried oxide is greater than 65 nm and that of the silicon is greater than 40 nm. The back controls are formed by implantation, which implies a doping of the channels of the CMOS device, which disrupts the operation of these channels (more complicated adjustment of threshold voltages may be helpful). The charges placed in the dielectric following the implantation may modify the electrostatic coupling effects, which may have an impact on the short channel effects of the CMOS device. In addition, the doped zones of the back controls extend uniquely underneath the active zones of the transistors, making the connection of the back controls complex.
The document “65 nm High Performance SRAM Technology with 25F2, 0.16 μm2 S3 (Stacked Single-crystal Si) SRAM Cell, and Stacked Peripheral SSTFT for Ultra High Density and High Speed Applications” of Hoon Lim et al., Proceedings of ESSDERC, 2005, pages 549 to 552, discloses an architecture comprising MOS transistors stacked upon each other on three levels. This type of architecture enables a gain in the integration density of the transistors (less occupied space), but this gain implies a greater complexity of the method to fabricate such a structure (multiplication of photolithography steps necessary for forming the gates of the transistors). In addition, the stacked transistors of the SOI device may not be optimized since their buried oxide layer is thick and it may be difficult to improve the performance by a back control. The optimal crystalline orientation for this device may be achievable by bonding. Finally, the polycrystalline silicon deposited may helpfully be recrystallised, implying a long thermal budget at low temperature or several bonding steps, increasing the fabrication cost of this device.